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Waveform-intensive applications like sonar, radar and SIGINT seem to have an endless appetite for signal processing power. Faster DSPs coupled with a broader range of IP cores and development tools for FPGAs are joining forces to form new DSP system architectures. Using those building blocks, board-level subsystems must quickly acquire and process massive amounts of data in real time.
As FPGAs evolve to ever greater sophistication, complete systems can now be integrated into one or more FPGAs. As a result, the rack and backplane-based systems based on FPGAs offer the compute muscle of yesterday’s supercomputers. Modern radar systems are operating over an ever increasing frequency range. Analog conversion technology–both A/D and D/A converters–are also feeding the radar needs of the military.
System developers can now build radar receiver systems with a higher instantaneous bandwidth thanks to the converters, and can handle the corresponding increase in compute power required to process the received data streams using FPGAs. The ASIC-based radar design approaches of the past can achieve the performance needed, but that path lacks the flexibility inherent in designs based on FPGA technology. A wealth of FPGA board-level products are available aimed specifically at this area.
Exemplifying this trend, TEK Microsystems offers a 6U VITA 41-compliant dual-channel high-speed digitizer board called Neptune-V5 (Figure 1). The board sports three Virtex-5 processors, advanced DDR3 SDRAM, and the latest flexible I/O communication modules (SFP+ and QSFP). Full ruggedization has been designed into the architecture providing full support for harsh environments. Firmware and software support for a range of open standards and protocols is provided including Gbit Ethernet, Serial FPDP (ANSI VITA 17.1 and 17.2) and Fibre Channel.
Fast Sensor I/O Interfacing
For inter-FPGA and inter-board communications, protocol support is provided for Xilinx Aurora and PCI Express. The approach to the architecture focuses on the sensor I/O processing and allows it to more efficiently utilize three V-5 processors than competitive offerings of up to seven FPGAs, resulting in a lower price point and reduced power consumption. A very broad range of analog sensor I/O configurations provides compatibility with the widest range of analog signal options, addressing multi-channel, high-resolution sampled data requirements at 2 Gsamples/s and beyond.
Nallatech’s latest FPGA product aims at using FPGAs for Intel Front Side Bus (FSB) acceleration. The FSB Compute Module enables up to 660K logic cells per module by utilizing two large Xilinx Virtex-5 FPGAs that are user configured to host the accelerated algorithm. The modular platform includes an FSB Base Module that interfaces directly to an Intel Xeon processor socket.
FPGA-Based Mezzanine Form Factor
FPGAs have become such a key part of the embedded computing landscape that they’ve even captured their own form factor spec. The FPGA Mezzanine Card (FMC) specification–VITA 57–defines an I/O mezzanine module designed to work intimately with an FPGA. FMC modules enable I/O devices that reside on an industry standard (VITA 57) mezzanine card to be attached to, and directly controlled by FPGAs that reside on a host board. About half the size of a PMC mezzanine module, FMCs provide a small footprint, reduced I/O bottlenecks, increased flexibility, and reduced cost through the elimination of redundant interfaces. To maximize data throughput and minimize latency, the FMC connector provides numerous I/O pins that support high-speed signals for moving data between the FMC and the FPGA. The FMC specification was developed to enable FMCs to be supported on a wide range of existing form factors, including but not limited to VME, CompactPCI, VXS, VPX, VPX-REDI, CompactPCI Express, AdvancedTCA and AMC.
Fueled by its acquisition of VMETRO–the creator of the FMC concept–Curtiss-Wright this month rolled out its highest sampling rate, highest bandwidth FPGA Mezzanine Card (FMC/VITA 57) module, the ADC512 (Figure 2), a 3 Gsamples/s 8-bit, dual-channel analog-to-digital converter (ADC) card, able to support up to 6 Gbyte/s data throughput. The module eliminates data bottlenecks to increase DSP subsystem performance by routing high-speed ADC I/O directly to the host board’s FPGAs via the FMC connector. Available in both air-cooled and conduction-cooled rugged versions, the ADC512 has two onboard National Semiconductor ADC083000 ADC devices. Each of the module’s ADCs supports a sampling rate up to 3000 Msamples/s per channel. By routing the ADC device interfaces directly to the FMC connector, the ADC512 enables an FPGA on the host board to directly control and receive data.
FPGA ICs Push Density, Performance Barriers
On the component side, last fall Xilinx rolled out its Virtex-5 FXT devices, the industry’s first FPGAs with embedded PowerPC 440 processor blocks, high-speed RocketIO GTX transceivers and dedicated XtremeDSP processing capabilities. The Virtex-5 FXT platform offers the first FPGAs to provide up to two industry-standard PowerPC 440 processor blocks. Each processor, with integrated 32 Kbyte instruction and 32 Kbyte data caches, delivers up to 1,100 DMIPS at 550 MHz. Tightly coupled to the PowerPC440 blocks is a new integrated 5x2 cross bar processor interconnect architecture that provides simultaneous access to I/O and memory. The device includes dedicated master and slave processor local bus interfaces, four DMA ports with separate transmit and receive channels, and a dedicated memory bus interface enabling high-performance, low-latency, point-to-point connectivity.
Altera, meanwhile, began shipping its new 40nm Stratix IV FPGAs in December. The first device available was the EP4SGX230, offering 230K logic elements (LEs), 36 embedded transceivers operating up to 8.5 Gbits/s, 17 Mbits of RAM and 1,288 embedded multipliers. The Stratix IV FPGA family is comprised of two variants, an enhanced (E) version and transceiver-based (GX) version. The Stratix IV family offers up to 680K logic elements. The devices also support DDR3 memory interface speeds of 1067 Mbits/s. Stratix IV GX FPGAs feature up to 48 transceivers operating up to 8.5 Gbits/s. They also incorporate up to four hard IP cores for PCIe Gen1 and Gen2 (x1, x4 and x8), and support a wide range of protocols including Serial RapidIO, Gbit Ethernet, XAUI, CPRI (including 6G CPRI), CEI 6G, GPON, SFI-5.1 and Interlaken.
FPGAs and ADCs Working Together
Analog converter technology is also fueling new radar capabilites, especially when used hand in hand with advanced FPGAs. Last fall Texas Instruments debuted its new ADS5485 A/D Converter. Four of these 200 MHz, 16-bit monolithic A/Ds were designed in the front end of Pentek’s Model 7153 PMC board (Figure 3). These new A/Ds exhibit a signal-to-noise ratio of 75 dBFS and a spurious-free dynamic range of 87 dBc at a 70 MHz input frequency.
The Model 7153 DDC offers two modes of operation. The two-channel DDC mode sacrifices two DDC channels to boost the maximum decimation to 65,536 and extend the lower bandwidth limit down to 3 kHz. The four-channel DDC mode provides an independently programmable decimation range from 2 to 256 on each DDC, covering signal bandwidths from about 700 kHz to 90 MHz.
In applications such as radar, direction finding and diversity receivers, it is essential to synchronize multiple channels, perform digital downconversion, control the gain and the phase delay of each channel and then perform a summation of the DDC outputs. All of these critical beamforming facilities are included in the Model 7153. In addition to synchronous sampling and DDC for all four channels, the 7153 provides independent control of gain and phase for each DDC, and includes a summation block for the four DDC outputs.
San Jose, CA.
Annapolis Micro Systems Inc
Curtiss-Wright Controls Embedded Computing
Upper Saddle River, NJ.
San Jose, CA.