Over the last 20 years, military embedded systems developers have struggled to balance two trends: increased functionality vs. standard off-the-shelf products. As chip suppliers provide more and more capability within a smaller size, weight and power envelope, the amount of functionality that can be packed onto a single 6U VME-type card gets higher and higher. Unfortunately, the mechanical constraints of the backplane and front panel have not grown as quickly, making it difficult to create a single off-the-shelf product that meets every system’s requirements, particularly when it comes to I/O interfaces. While it is possible to create a range of similar board designs with different options, this works against the potential cost savings of standardization and can increase system integration complexity.

In the early 1990s, board suppliers started to address this problem through the use of “daughtercards” or mezzanine I/O modules. By designing a carrier card with the core processing and memory components and using one or more separate mezzanine cards for I/O, board suppliers could offer off-the-shelf products with a user-configurable set of I/O functions. As this approach gained traction, industry standards such as IP Modules (ANSI/VITA 4-1995), PCI Mezzanine Card (PMC, or IEEE 1386.1-2001) and Switched Mezzanine Card (XMC, or ANSI/VITA 42-2008) were developed, in each case enabling ecosystems of interoperable modules and carrier cards from multiple suppliers.

The Open Standard Trade-off

Open standards are valuable when the critical mass for an ecosystem exists, but they necessarily sacrifice highly optimized performance in specific applications to support the widest possible range of requirements. When the performance requirements are less demanding, the value of the ecosystem (more competition, wider range of options, lower costs) exceeds the limitations imposed by the standard and so the trade-off is acceptable to the defense marketplace. However, when an application needs very high throughput, efficiency, or power/thermal performance, the limitations of a least-common-denominator standard may not be viable.

One application area where this is particularly true is in high-performance A/D and D/A conversion. The signal integrity and throughput requirements for multichannel acquisition and processing are difficult to implement efficiently using standards-based mezzanine designs, and the power and thermal requirements of multi-gigasample per second (Gsample/s) converters are in some cases beyond what is possible using standard mezzanines, particularly for deployed environments.

While open standards are desirable in principle, a single vendor solution such as the QuiXmodule architecture has some key advantages over a generic approach. Because the mezzanine and carrier cards are always shipped as an integrated unit, the cold plate is a single machined component designed for optimum thermal transfer from the specific mezzanine and carrier card being used. The mezzanine-to-carrier power and electrical interface is also configured appropriately for the specific interface being implemented, and the firmware interface between the A/D and the FPGA is optimized for throughput while enabling multi-channel synchronization across boards. If an open-standard interface was being used, it would by necessity be more general purpose and would be hard pressed to meet the mechanical, power, thermal and electrical performance characteristics of the more application-specific implementation used by each QuiXmodule.

High-performance signal processing systems are typically driven by the combination of sample rate, resolution and channel count. As each of these parameters increases, the total throughput from the mezzanine to the carrier card goes up, and the power dissipated on the mezzanine for the A/D itself also rises. A typical configuration might use eight 12-bit channels at 1 Gsample/s in a single 6U card, resulting in throughput of 12 Gbytes/s (8 x 12-bits x 1 GHz = 96 Gbits/s = 12 Gbytes/s) and total A/D power of 30W.

For signal acquisition, raw resolution and bandwidth are only effective if the analog front end and the acquisition subsystem maintain good signal integrity as the signal is moved into the digital domain for processing. The use of a mezzanine card potentially helps this problem as the analog components are physically on a separate card from the digital processing components on the carrier card. However, even with the best design practices on the mezzanine card portion of the design, it is still necessary for the carrier card to avoid placing high-speed components underneath the mezzanine and to take other steps to make sure that the integrated assembly maintains good analog performance. These aspects of the design are typically not addressed by industry standards, which are designed for both analog and non-analog interfaces, making it difficult to reliably integrate mezzanine I/O modules and carrier cards together without sacrificing analog signal quality.