Page 1 of 1
A new 12-bit ADC supports either two 12-bit analog-to-digital converter (ADC) channels at 3.2 GSPS (Gigasamples per second) or six channels at 1.6 GSPS. The Calypso-V5 from Tekmicro is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS-based systems and combines high-density FPGA processing with the ultimate in ultra wide band ADC signal acquisition. Calypso-V5 is based on the latest National Semiconductor ADC device, which supports either a pair of channels in non-interleaved mode or a single channel using 2:1 interleaved sampling. Calypso-V5 contains four ADC devices, supporting a total of either six channels plus trigger at 1.6 GSPS or two channels plus trigger at 3.2 GSPS.
In all modes, the converters provide 12-bit resolution and open analog bandwidth exceeding 2 GHz. This allows Calypso-V5 to be used as a 3.2 GSPS converter for 1st Nyquist applications or as a high-density multichannel building block for lower bandwidth applications using either 1st or 2nd Nyquist sampling. Calypso-V5 also includes sample-accurate trigger synchronization in all modes, allowing coherent processing of multiple input channels both within a single card and across multiple cards. This allows applications of up to 108 channels to be supported within a single chassis. The Calypso-V5 contains four separate ADC devices, with each pair of devices assigned to its own front-end FPGA for signal processing. In the QuiXilica-V5 family, the front-end FPGA is typically a Xilinx Virtex-5 SX95T-2 device. Future QuiXilica products later in 2010 will offer higher density Virtex-6 FPGA options including LX240T, SX315T and SX475T devices. The two front-end FPGAs are supplemented with a “back-end” FPGA, which can be used for additional processing or for backplane or front panel communications. In the QuiXilica-V5 family, the back-end FPGA can be configured with a range of Xilinx Virtex-5 FPGA options, from the standard LX110T-2 up to a LX330T, FX200T, or SX240T, depending on application requirements.